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Instruction-Level Parallelism (ILP) • instruction overlap in a pipeline • executing instructions in parallel (but it is visible to the architecture) Superscalar vs Superpipeline Instruction Level Parallelism • Instruction level parallelism is the degree on average by which the instruction of a program can be executed in parallel • Achieved by: —Compiler based optimization —Hardware techniques • Limited by: —True data dependency —Procedural dependency —Resource conflicts

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CS 207 D Computer Architecture. – Kai Hwang & F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, 1989 –Instruction level parallelism and machine parallelism, Computer Architecture: SIMD/Vector/GPU Exploiting Regular (Data) Parallelism SIMD exploits instruction-level parallelism.

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– Kai Hwang & F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, 1989 –Instruction level parallelism and machine parallelism Computer Architecture: SIMD and GPUs (Part I) Computer Architecture, SIMD exploits instruction-level parallelism

Instruction-Level Parallelism (ILP) • instruction overlap in a pipeline • executing instructions in parallel (but it is visible to the architecture) Computer Architecture: SIMD/Vector/GPU Exploiting Regular (Data) Parallelism SIMD exploits instruction-level parallelism

Instruction-Level Parallelism • Instruction-Level Parallelism (ILP) – Overlap the execution of instructions to improve performance • 2 approaches to exploit ILP 1. Rely on hardware to help discover and exploit the parallelism dynamically – Pentium 4, AMD Opteron, IBM Power 2. Rely on software technology to find parallelism, statically at compile-time Instruction-level Parallelism in Prolog: Analysis and Architectural Support. Computer Architecture, Instruction-level Parallelism in Prolog:

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